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jyt to website enGraduates2026.06.01
Role Overview
Design compiler technologies that translate AI models into optimized code for the RISC-V AI SoC. You will focus on IR design, code generation, autotuning, and ensuring clean integration with upstream toolchains (LLVM, MLIR, TVM).
Key Responsibilities
1. Extend MLIR/LLVM to support vector and matrix instruction sets.
2. Implement optimization and lowering passes for AI operators.
3. Build compiler interfaces compatible with ecosystem conventions.
4. Integrate autotuning and performance modeling.
5. Collaborate with runtime and kernel teams to align code generation strategies.
Qualifications
1. 4+ years in compiler backend or performance optimization.
2. Strong C++/Python proficiency.
3. Familiarity with MLIR, LLVM, TVM, or XLA.
Preferred Attributes
1. Experience integrating custom instructions or intrinsics
2. Knowledge of AI model graph-to-code lowering workflows.
3. Familiarity with autotuning systems like AutoTVM or MLIR-based tuners.
4. Understanding of mixed-precision compute and performance trade-offs.
Impact: You enable portable, high-performance compilation pipelines that power ecosystem integration.
recruit.sgpr@espressif.com

